\hypertarget{struct_uart_init_reg_def}{
\section{UartInitRegDef Struct Reference}
\label{struct_uart_init_reg_def}\index{UartInitRegDef@{UartInitRegDef}}
}


Initializes the structure of uart parameters.  




{\ttfamily \#include $<$uart.h$>$}

\subsection*{Data Fields}
\begin{DoxyCompactItemize}
\item 
u16\_\-t \hyperlink{struct_uart_init_reg_def_adc3bb27875076e41257bca725e3b5813}{USART\_\-BaudRate}
\item 
u16\_\-t \hyperlink{struct_uart_init_reg_def_a17b9b03af7c3a6b37e58db30132d45a7}{USART\_\-WordLength}
\item 
u16\_\-t \hyperlink{struct_uart_init_reg_def_a3881a533e8753cad0479062228110218}{USART\_\-StopBits}
\item 
u16\_\-t \hyperlink{struct_uart_init_reg_def_a4a87bf8bc5147b8c34553c2f605e0f4e}{USART\_\-Parity}
\item 
u16\_\-t \hyperlink{struct_uart_init_reg_def_a3f929d492530b336d098311ddfc8c058}{USART\_\-Mode}
\item 
u16\_\-t \hyperlink{struct_uart_init_reg_def_aca951d39d66ba6ca67ae78897be19a6c}{USART\_\-HardwareFlowControl}
\item 
u16\_\-t \hyperlink{struct_uart_init_reg_def_ab78244b4c790cd14f2e4d535f1303a4f}{USART\_\-TXLen}
\item 
u16\_\-t \hyperlink{struct_uart_init_reg_def_a430bbb7b07f0b0c335875a92ba62707f}{USART\_\-RXLen}
\item 
u16\_\-t \hyperlink{struct_uart_init_reg_def_a9b621aab38c4794ad11fadf0a4cef3dd}{USART\_\-TXaddr}
\item 
u16\_\-t \hyperlink{struct_uart_init_reg_def_ae6f63e672cca5ace2d248c2e7cbb797b}{USART\_\-RXaddr}
\end{DoxyCompactItemize}


\subsection{Detailed Description}
Initializes the structure of uart parameters. 

\subsection{Field Documentation}
\hypertarget{struct_uart_init_reg_def_adc3bb27875076e41257bca725e3b5813}{
\index{UartInitRegDef@{UartInitRegDef}!USART\_\-BaudRate@{USART\_\-BaudRate}}
\index{USART\_\-BaudRate@{USART\_\-BaudRate}!UartInitRegDef@{UartInitRegDef}}
\subsubsection[{USART\_\-BaudRate}]{\setlength{\rightskip}{0pt plus 5cm}u16\_\-t {\bf USART\_\-BaudRate}}}
\label{struct_uart_init_reg_def_adc3bb27875076e41257bca725e3b5813}
UART baud rate divisor by uart clock \hypertarget{struct_uart_init_reg_def_aca951d39d66ba6ca67ae78897be19a6c}{
\index{UartInitRegDef@{UartInitRegDef}!USART\_\-HardwareFlowControl@{USART\_\-HardwareFlowControl}}
\index{USART\_\-HardwareFlowControl@{USART\_\-HardwareFlowControl}!UartInitRegDef@{UartInitRegDef}}
\subsubsection[{USART\_\-HardwareFlowControl}]{\setlength{\rightskip}{0pt plus 5cm}u16\_\-t {\bf USART\_\-HardwareFlowControl}}}
\label{struct_uart_init_reg_def_aca951d39d66ba6ca67ae78897be19a6c}
1: enable RTS/CTS flow control;0:disable RTS/CTS flow control \hypertarget{struct_uart_init_reg_def_a3f929d492530b336d098311ddfc8c058}{
\index{UartInitRegDef@{UartInitRegDef}!USART\_\-Mode@{USART\_\-Mode}}
\index{USART\_\-Mode@{USART\_\-Mode}!UartInitRegDef@{UartInitRegDef}}
\subsubsection[{USART\_\-Mode}]{\setlength{\rightskip}{0pt plus 5cm}u16\_\-t {\bf USART\_\-Mode}}}
\label{struct_uart_init_reg_def_a3f929d492530b336d098311ddfc8c058}
1: enable half duplex single line UART;0:enable duplex line UART \hypertarget{struct_uart_init_reg_def_a4a87bf8bc5147b8c34553c2f605e0f4e}{
\index{UartInitRegDef@{UartInitRegDef}!USART\_\-Parity@{USART\_\-Parity}}
\index{USART\_\-Parity@{USART\_\-Parity}!UartInitRegDef@{UartInitRegDef}}
\subsubsection[{USART\_\-Parity}]{\setlength{\rightskip}{0pt plus 5cm}u16\_\-t {\bf USART\_\-Parity}}}
\label{struct_uart_init_reg_def_a4a87bf8bc5147b8c34553c2f605e0f4e}
1: odd parity; 0: even parity \hypertarget{struct_uart_init_reg_def_ae6f63e672cca5ace2d248c2e7cbb797b}{
\index{UartInitRegDef@{UartInitRegDef}!USART\_\-RXaddr@{USART\_\-RXaddr}}
\index{USART\_\-RXaddr@{USART\_\-RXaddr}!UartInitRegDef@{UartInitRegDef}}
\subsubsection[{USART\_\-RXaddr}]{\setlength{\rightskip}{0pt plus 5cm}u16\_\-t {\bf USART\_\-RXaddr}}}
\label{struct_uart_init_reg_def_ae6f63e672cca5ace2d248c2e7cbb797b}
UART RX DMA start address pointer \hypertarget{struct_uart_init_reg_def_a430bbb7b07f0b0c335875a92ba62707f}{
\index{UartInitRegDef@{UartInitRegDef}!USART\_\-RXLen@{USART\_\-RXLen}}
\index{USART\_\-RXLen@{USART\_\-RXLen}!UartInitRegDef@{UartInitRegDef}}
\subsubsection[{USART\_\-RXLen}]{\setlength{\rightskip}{0pt plus 5cm}u16\_\-t {\bf USART\_\-RXLen}}}
\label{struct_uart_init_reg_def_a430bbb7b07f0b0c335875a92ba62707f}
UART Rx DMA buffer size \hypertarget{struct_uart_init_reg_def_a3881a533e8753cad0479062228110218}{
\index{UartInitRegDef@{UartInitRegDef}!USART\_\-StopBits@{USART\_\-StopBits}}
\index{USART\_\-StopBits@{USART\_\-StopBits}!UartInitRegDef@{UartInitRegDef}}
\subsubsection[{USART\_\-StopBits}]{\setlength{\rightskip}{0pt plus 5cm}u16\_\-t {\bf USART\_\-StopBits}}}
\label{struct_uart_init_reg_def_a3881a533e8753cad0479062228110218}
\hypertarget{struct_uart_init_reg_def_a9b621aab38c4794ad11fadf0a4cef3dd}{
\index{UartInitRegDef@{UartInitRegDef}!USART\_\-TXaddr@{USART\_\-TXaddr}}
\index{USART\_\-TXaddr@{USART\_\-TXaddr}!UartInitRegDef@{UartInitRegDef}}
\subsubsection[{USART\_\-TXaddr}]{\setlength{\rightskip}{0pt plus 5cm}u16\_\-t {\bf USART\_\-TXaddr}}}
\label{struct_uart_init_reg_def_a9b621aab38c4794ad11fadf0a4cef3dd}
UART TX DMA start address pointer \hypertarget{struct_uart_init_reg_def_ab78244b4c790cd14f2e4d535f1303a4f}{
\index{UartInitRegDef@{UartInitRegDef}!USART\_\-TXLen@{USART\_\-TXLen}}
\index{USART\_\-TXLen@{USART\_\-TXLen}!UartInitRegDef@{UartInitRegDef}}
\subsubsection[{USART\_\-TXLen}]{\setlength{\rightskip}{0pt plus 5cm}u16\_\-t {\bf USART\_\-TXLen}}}
\label{struct_uart_init_reg_def_ab78244b4c790cd14f2e4d535f1303a4f}
UART Tx DMA buffer size \hypertarget{struct_uart_init_reg_def_a17b9b03af7c3a6b37e58db30132d45a7}{
\index{UartInitRegDef@{UartInitRegDef}!USART\_\-WordLength@{USART\_\-WordLength}}
\index{USART\_\-WordLength@{USART\_\-WordLength}!UartInitRegDef@{UartInitRegDef}}
\subsubsection[{USART\_\-WordLength}]{\setlength{\rightskip}{0pt plus 5cm}u16\_\-t {\bf USART\_\-WordLength}}}
\label{struct_uart_init_reg_def_a17b9b03af7c3a6b37e58db30132d45a7}
UART Data length 1: 9 bits; 0: 8 bits 

The documentation for this struct was generated from the following file:\begin{DoxyCompactItemize}
\item 
uart.h\end{DoxyCompactItemize}
